New Cadence Incisive Formal Verifier Extends the Power of Formal Analysis to Designers' Desktops; Designers Benefit from Improved Productivity and Increased Quality of Functional Verification
SAN JOSE, Calif.—(BUSINESS WIRE)—May 2, 2005—
Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN)
today announced the release of the Incisive(TM) Formal Verifier,
extending the power of formal analysis to designers' desktops.
Combined with Cadence simulation, acceleration and emulation
technologies, the Incisive Formal Verifier enables designers to
improve the productivity and quality of functional verification
earlier in the design and verification process. Customers can reduce
production schedules significantly because design engineers can begin
verification as they are designing the chip.
An integral part of the Incisive verification platform's
assertion-based verification (ABV) offering, formal analysis does not
require a set of test vectors, which means functional bugs can be
detected months before testbench development and simulation.
Incorporating Formal Verifier into verification flows can help
minimize silicon re-spins and improve the quality of design. Formal
analysis methods can statically expose corner-case functional bugs
that are difficult -- sometimes impossible -- to detect with dynamic
verification techniques like simulation, acceleration or emulation.
"We conducted an extensive evaluation of leading static property
checkers and chose the Incisive Formal Verifier for production flow
adoption," said Bernd Zombek, project manager, Siemens. "It enables us
to begin verification months before the testbench is ready, which
improves productivity for our design and verification teams. Incisive
Formal Verifier is easy to adopt and almost anyone can use it after
some basic assertion training."
Incisive Formal Verifier employs the same set of assertions
supported across the entire Incisive platform. With this broad
support, designers can begin writing and verifying assertions using
formal analysis prior to simulation. As the blocks are integrated, the
same assertions can be used in the Incisive Unified Simulator and
later in the Incisive Palladium II accelerator/emulator, enabling a
continuous, synergistic flow throughout the entire platform. While
Formal Verifier works synergistically with Incisive Unified Simulator,
it can also be deployed in flows that use other simulators.
Incisive Formal Verifier supports designs using Verilog,
SystemVerilog, VHDL and mixed-language environments, with assertions
written in PSL and SVA, or using OVL and the Incisive Assertion
Library. A wide range of complementary leading-edge formal engines is
provided, along with automatic assertion extraction, formal coverage
metrics, and advanced usability and debug features.
"The introduction of the Incisive Formal Verifier product
represents an evolutionary change in how designers will design and
verify large, complex chips," said Mitch Weaver, vice president and
general manager, Systems and Functional Verification, Cadence.
"Functional verification has been a significant challenge in the
chip-design process and having the ability to formally verify
assertions substantially increases our customers' productivity, while
improving the quality of the design."
The Incisive Formal Verifier has already been deployed by several
key customers and is currently available to the general public. For
more information, please visit:
www.cadence.com/company/newsroom/press_kits/index.aspx.
About Cadence
Cadence is the world's largest supplier of electronic-design
technologies and engineering services. Cadence products and services
are used to accelerate and manage the design of semiconductors,
computer systems, networking equipment, telecommunications equipment,
consumer electronics, and other electronics-based products. With
approximately 4,900 employees and 2004 revenues of approximately $1.2
billion, Cadence has sales offices, design centers, and research
facilities around the world. The company is headquartered in San Jose,
Calif., and trades on both the New York Stock Exchange and Nasdaq
under the symbol CDN. More information is available at
www.cadence.com.
Contact:
Cadence Design Systems, Inc.
Ric Chope, 650-934-6820
ricchope@cadence.com
